Thresholding Data

Denormal numbers are the border values in the floating-point format and special case values for the processor. Denormal data occurs, for example, in filtering by Infinite Impulse Response (IIR) and Finite Impulse Response (FIR) filters of the signal captured in fixed-point format and converted to the floating-point format. Operations on denormal data make processing slow, even if corresponding interrupts are disabled. To avoid the slowdown effect in denormal data processing, the Intel IPP threshold functions can be applied to the input signal before filtering. For example:

     if (denormal_data)

      ippsThreshold_LT_32f_I( src, len, 1e-6f );

     ippsFIR_32f( src, dst, len, st );

The 1e-6f value is the threshold level; the input data below that level are set to zero. Because the Intel IPP threshold function is very fast, the execution of these two functions is faster than execution of filter if denormal numbers meet in the source data. Of course, if the denormal data occurs while using the filtering procedure, the threshold functions do not help.

For Intel(R) Pentium(R) 4 processor and later processors, you can set special computation modes - flush-to-zero (FTZ) and the denormals-are-zero (DAZ). Use the functions ippSetFlushToZero and ippSetDenormAreZeros to enable these modes. Note that this setting takes effect only when computing is done with the Intel(R) Streaming SIMD Extensions (Intel(R) SSE) and Intel(R) Streaming SIMD Extensions 2 (Intel(R) SSE2) instructions. (See more details http://software.intel.com/en-us/articles/x87-and-sse-floating-point-assists-in-ia-32-flush-to-zero-ftz-and-denormals-are-zero-daz/).

The following table illustrates how denormal data may affect performance and shows the effect of thresholding denormal data. As you can see, thresholding takes only three clocks more. On the other hand, denormal data can cause the application performance to drop x250.

Performance Resulting from Thresholding Denormal Data

Data/Method

Normal

Denormal

Denormal +

Threshold

CPU cycles per element

46

11467

49

Optimization Notice

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804


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