Reusing Buffers

Some Intel IPP functions require internal memory for various optimization strategies. However, memory allocation inside of the function may have a negative impact on performance in some situations, for example, cache misses. To avoid or minimize memory allocation and keep your data in a warm cache, some functions, for example, Fourier transform functions (FFT), can use or reuse memory given as a parameter to the function.

If you call such a function, many times, you can reuse of an external buffer and get better performance.

The following example reuses memory buffers to compute FFT as two FFTs in two separate threads:

            
ippsFFTInitAlloc_C_32fc(&ctxN2, order-1, IPP_FFT_DIV_INV_BY_N, ippAlgHintAccurate);      
ippsFFTGetBufSize_C_32fc( ctxN2, &sz );

buffer = sz > 0 ? ippsMalloc_8u( sz ) : 0;

/// prepare source data for two FFTs                       
int phase = 0;                        
ippsSampleDown_32fc( x, fftlen, xleft, &fftlen2, 2, &phase );                        
phase = 1;                        
ippsSampleDown_32fc( x, fftlen, xrght, &fftlen2, 2, &phase );
                               
ippsFFTFwd_CToC_32fc( xleft, Xleft, ctxN2, buffer );                        
ippsFFTFwd_CToC_32fc( xrght, Xrght, ctxN2, buffer );

The external buffer is not necessary. If the pointer to the buffer is 0, the function allocates memory inside.

Optimization Notice

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804


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