Static Linking without Dispatching

Static linking links directly with the merged static libraries. Use this method to link a self contained application that is supported on a specific processor type. Static linking is useful for embedded applications that are bundled with one type of processor.

The following table summarizes the features of static linking to help you understand the benefits and drawbacks of this linking method.

**Summary of Features of the Static Linking (without dispatching)**
Benefits	Drawbacks
Small executable size with support for only one processor type Suitable for kernel-mode/device-driver/ring-0 use *) Suitable for a Web applet or a plug-in requiring very small file download and support for only one processor type Self-contained application executable that does not require the Intel IPP run-time SOs Smallest footprint for application package Smallest installation package	The executable is optimized for only one processor type Updates to processor-specific optimizations require rebuild and/or relink

*) for unthreaded non-PIC libraries only

You may want to use your own static dispatcher instead of the provided emerged dispatcher. The IPP sample mergelib demonstrates how to do this.

Refer to the latest updated sample from the Intel IPP samples directory: /ipp-samples/advanced-usage/linkage/mergelib at http://www.intel.com/software/products/ipp/samples.htm.

The Intel IPP package includes a set of processor-specific header files (such as ipp_v8.h). You can use these header files instead of the IPPCALL macro. Refer to Static linking to Intel(R) IPP Functions for One Processor in /ipp/tools/<arch>/static.lib/readme.htm.

Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804

Optimization Notice

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804