Dispatching

Intel IPP uses codes optimized for various central processing units (CPUs). Dispatching refers to detection of your CPU and selecting the corresponding Intel IPP binary. For example, the libippiv8.so.7.0 file in the /ipp/lib/ia32 directory, reflects the imaging processing libraries optimized for the Intel(R) Core™ 2 Duo processors.

A single Intel IPP function, for example ippsCopy_8u(), may have many versions, each one optimized to run on a specific Intel(R) processor with specific architecture, for example, the version of this function optimized for the Intel(R) Core™ 2 Duo processor is v8_ippsCopy_8u(), and version optimized for 64-bit applications on processors with Intel(R) SSE4.1 is u8_ippsCopy_8u().

The following table shows processor-specific codes used in Intel IPP:

Identification of Codes Associated with Processor-Specific Libraries
Abbreviation	Meaning
IA-32 Intel® architecture
px	C-optimized for all IA-32 processors
v8	Optimized for processors with Intel® Supplemental Streaming SIMD Extensions 3
p8	Optimized for processors with Intel® Streaming SIMD Extensions 4.1
g9	Optimized for processors that support Intel® Advanced Vector Extensions instruction set
s8	Optimized for the Intel® Atom™ processor
Intel® 64 architecture
mx	C-optimized for processors with Intel® 64 instructions set architecture
u8	Optimized for 64-bit applications on processors with Intel® Supplemental Streaming SIMD Extensions 3
y8	Optimized for 64-bit applications on processors with Intel® Streaming SIMD Extensions 4.1
n8	Optimized for the Intel® Atom™ processor
e9	Optimized for processors that support Intel® Advanced Vector Extensions instruction set

Supporting Intel(R) Xeon(R) Processors with the Intel(R) 64 Architecture

Intel IPP supports Intel(R) Xeon(R) processors with the Intel(R) 64 architecture running 32-bit and 64-bit modes. For the 32-bit mode, download and install Intel IPP for the Pentium(R) processor-based systems. When running the 64-bit mode, install Intel IPP for the Intel(R) 64 architecture.

Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804

Optimization Notice

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804