SAD16x16xN, SAD16x16xNI

Syntax

IppStatus ippiSAD16x16xN_8u16u_C1R(const Ipp8u* pSrc, Ipp32s srcStep, const Ipp8u* pRef, Ipp32s refStep, Ipp16u* pSAD, Ipp32s numSAD);

IppStatus ippiSAD16x16xNI_8u16u_C1R(const Ipp16u* pSrc, Ipp32s srcStep, const Ipp16u* pRef, Ipp32s refStep, Ipp16u* pSAD, Ipp32s numSAD, Ipp32u* pMinSADIndex);

Parameters

pSrc	Pointer to the current block of specified size.
srcStep	Distance in bytes between starts of the consecutive lines in the source image.
pRef	Pointer to the reference block of specified size.
refStep	Distance in bytes between starts of the consecutive lines in the reference image.
pSAD	Pointer to an array of numSAD size to store calculated results.
numSAD	Number of SAD to calculate; should be a product of 8.
pMinSADIndex	Index of the minimal SAD value in pSAD array.

Description

These functions are declared in the ippvc.h header file. The functions ippiSAD16x16xN_8u16u_C1R and ippiSAD16x16xNI_8u16u_C1R calculate a series of sums of absolute difference between all the elements in the current block and the corresponding elements in the reference block and store the results in the given array. The functions use the SSE4.1 instructions to enhance motion estimation.

Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804

Optimization Notice

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804

See below for a figure that illustrates operation of the functions.

Operation of ippiSAD16x16xN_8u16u_C1R and ippiSAD16x16xNI_8u16u_C1R

Return Values

ippStsNoErr	Indicates no error.
ippStsNullPtrErr	Indicates an error when at least one input pointer is NULL.
ippStsStepErr	Indicates an error if the number of SADs to produce is not a product of 8.