OpenMP* Fortran Compiler Directives

Intel® Fortran provides OpenMP* Fortran compiler directives that comply with OpenMP Fortran Application Program Interface (API) specification Version 1.1 and most of Version 2.0.

To use these directives, you must specify compiler option -openmp (Linux and Mac OS X) or /Qopenmp (Windows).

Options that use OpenMP* are available for both Intel® microprocessors and non-Intel microprocessors, but these options may perform additional optimizations on Intel® microprocessors than they perform on non-Intel microprocessors. The list of major, user-visible OpenMP constructs and features that may perform differently on Intel® microprocessors vs. non-Intel microprocessors includes: locks (internal and user visible), the SINGLE construct, barriers (explicit and implicit), parallel loop scheduling, reductions, memory allocation, thread affinity, and binding.

This section discusses data scope attribute clauses, conditional compilation rules, nesting and binding rules, and the following directives:

The OpenMP parallel directives can be grouped into the categories shown in the following table:

Categories of OpenMP Fortran Parallel Directives

Category

Description

Parallel region

Defines a parallel region: PARALLEL

Task region

Defines a task region: TASK

Work-sharing

Divide the execution of the enclosed block of code among the members of the team that encounter it: DO and SECTIONS

Combined parallel work-sharing

Shortcut for denoting a parallel region that contains only one work-sharing construct: PARALLEL DO and PARALLEL SECTIONS

Synchronization

Provide various aspects of synchronization; for example, access to a block of code, or execution order of statements within a block of code: ATOMIC, BARRIER, CRITICAL, FLUSH, MASTER, ORDERED, TASKWAIT, and TASKYIELD.

Data Environment

Control the data environment during the execution of parallel constructs: THREADPRIVATE

Note that certain general directives and rules can affect DO loops. For more information, see Rules for General Directives that Affect DO Loops.

Optimization Notice

Intel’s compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804

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